1. Field
This disclosure relates generally to data processing systems, and more specifically, to flow control mechanisms in a coherency interconnect.
2. Related Art
Increasingly complex on-chip interconnect micro-architectures have been developed, in part, to achieve higher data transfer bandwidths and/or lower latencies in system on a chip (SoC) designs. Typically, interconnect fabrics in accord with such micro-architectures seek to provide multi-path, point-to-point communications between a large and scalable set of processor cores, memory controllers, caches, direct memory access (DMA) controllers, bridges, etc. Coherency management techniques are employed to present a coherent system memory state while allowing multiple in-flight interconnect transactions to proceed concurrently in accordance with some appropriate total ordering of transactions. Basic storage operations such as reading or writing of storage locations, synchronization, etc. may be implemented using multiple transactions between two or more end-point devices.
As is well understood in the art, coherency in a multiprocessor system can involve complicated interactions between processor cores, their cache hierarchies and other devices. These interactions typically involve flows of interdependent transactions between entities. In some interconnect designs, particularly those that include a point-to-point interconnect matrix or pipelined busses, large numbers of in-flight transactions may share and compete for interconnect resources. In general, competition amongst transactions that are themselves subject to dependencies can create opportunities for deadlock. Although an impending deadlock can, in practice, often be avoided using retry techniques, frequent retries tend to sap system performance and, in any case, create scenarios that can be very hard to debug.
Techniques are desired to eliminate retries or at least avoid particular situations in which retries might otherwise be employed in a coherency interconnect.
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